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preliminary ftg for intel ? pentium ? 4 cpu and chipsets CY28323 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07004 rev. *b revised december 14, 2002 features ? compatible to intel ? ck-titan & ck-408 clock synthe- sizer/driver specifications system frequency synthesizer for intel brookdale 845 and brookdale - g pentium ? 4 chipsets programmable clock output frequency with less than 1 mhz increment integrated fail-safe watchdog timer for system recov- ery automatically switch to hw selected or sw pro- grammed clock frequency when watchdog timer time-out capable of generating system reset after a watchdog timer time-out occurs or a change in output frequency via smbus interface support smbus byte read/write and block read/ write operations to simplify system bios development vendor id and revision id support programmable drive strength support programmable output skew support power management control inputs available in 48-pin ssop cpu 3v66 pci ref 48m 24_48m x 3 x 4 x 10 x 2 x 1 x 1 intel and pentium are registered trademarks of intel corporation note: 1. signals marked with ? * ? and ? ^ ? has internal pull-up and pull-down resistors respectively. ~ block diagram pin configuration vdd_ref cpu0:1, cpu0:1#, xtal pll ref freq x2 x1 vdd_pci osc sclk pll 1 smbus logic vdd_48mhz sdata vdd_3v66 divider network vdd_cpu pll2 *fs0:4 2 pwr_dwn# ssop-48 ref0:1 vtt_pwrgd# *multsel1/ref1 vdd_ref x1 x2 gnd_pci *fs2/pci_f0 *fs3/pci_f1 pci_f2 vdd_pci *fs4/pci0 pci1 pci2 gnd_pci pci3 pci4 pci5 pci6 vdd_pci vtt_pwrgd# rst# gnd_48mhz *fs0/48mhz *fs1/24_48mhz vdd_48mhz 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 27 26 25 32 31 30 29 ref0/multsel0* gnd_ref vdd_cpu cpu_itp cpu_itp# gnd_cpu pwr_dwn# cpu0 cpu0# vdd_cpu cpu1 cpu1# gnd_cpu iref vdd_core gnd_core vdd_3v66 3v66_0 3v66_1 gnd_3v66 3v66_2 3v66_3 sclk sdata CY28323 *multsel0:1 3v66_0:3 pci_f0:2 pci0:6 48mhz 24_48mhz rst# cpu_itp, cpu_itp# [[1]]
preliminary CY28323 document #: 38-07004 rev. *b page 2 of 22 pin definitions pin name pin no. pin type pin description x1 3 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 4 o crystal connection: connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. ref0/multsel0 48 i/o reference clock 0/current multiplier selection 0: 3.3v 14.318-mhz clock out- put. this pin also serves as a power-on strap option to determine the current multiplier for the cpu clock outputs. the multsel1:0 definitions are as follows: multsel1:0 00 = ioh is 4 x iref 01 = ioh is 5 x iref 10 = ioh is 6 x iref 11 = ioh is 7 x iref ref1/multsel1 1 i/o reference clock 1/current multiplier selection 1: 3.3v 14.318-mhz clock out- put. this pin also serves as a power-on strap option to determine the current multiplier for the cpu clock outputs. the multsel1:0 definitions are as follows: multsel1:0 00 = ioh is 4 x iref 01 = ioh is 5 x iref 10 = ioh is 6 x iref 11 = ioh is 7 x iref cpu0:1, cpu0:1# 41, 38, 40, 37 o cpu clock outputs: frequency is set by the fs0:4 inputs or through serial input interface. cpu_itp, cpu_itp# 44, 45 i/o cpu clock output for itp: frequency is set by the fs0:4 inputs or through serial input interface. 3v66_0:3 31, 30, 28, 27 o 66-mhz clock outputs: 3.3v fixed 66-mhz clock. pci_f0/fs2 6 i/o free-running pci output 0/frequency select 2: 3.3v free-running pci output. this pin also serves as a power-on strap option to determine device operating frequency as described in the frequency selection table. pci_f1/fs3 7 i/o free-running pci output 1/frequency select 3: 3.3v free-running pci output. this pin also serves as a power-on strap option to determine device operating frequency as described in the table 4 . pci_f2 8 i/o free-running pci output 2: 3.3v free-running pci output. pci0/fs4 10 i/o pci output 0/frequency select 4: 3.3v pci output. this pin also serves as a power-on strap option to determine device operating frequency as described in table 4 . pci1:6 11, 12, 14, 15, 16, 17 o pci clock output 1 to 6: 3.3v pci clock outputs. 48mhz/fs0 22 i/o 48-mhz output/frequency select 0: 3.3v fixed 48-mhz, non-spread spectrum output. this pin also serves as a power-on strap option to determine device operating frequency as described in table 4 . this output will be used as the reference clock for usb host controller in intel 845 (brookdale) platforms. for intel brookdale - g platforms, this output will be used as the vch reference clock.
preliminary CY28323 document #: 38-07004 rev. *b page 3 of 22 24_48mhz/fs1 23 i/o 24- or 48-mhz output/frequency select 1: 3.3v fixed 24-mhz or 48-mhz non-spread spectrum output. this pin also serves as a power-on strap option to determine device operating frequency as described in table 4 . this output will be used as the reference clock for sio devices in intel 845 (brookdale) platforms. for intel brookdale - g platforms, this output will be used as the reference clock for both usb host controller and sio devices. we recom- mend system designer to configure this output as 48 mhz and ? high drive ? by setting byte [5], bit [0] and byte [9], bit [7], respectively. pwr_dwn# 42 i power down control: 3.3v lvttl-compatible input that places the device in power-down mode when held low. sclk 26 i smbus clock input: clock pin for serial interface. sdata 25 i/o smbus data input: data pin for serial interface. rst# 20 o (open- drain) system reset output: open-drain system reset output. iref 35 i current reference for cpu output: a precision resistor is attached to this pin which is connected to the internal current reference. vtt_pwrgd# 19 i powergood from voltage regulator module (vrm): 3.3v lvttl input. vtt_pwrgd# is a level-sensitive strobe used to determine when fs0:4 and multsel0:1 inputs are valid and ok to be sampled (active low). once vtt_pwrgd# is sampled low, the status of this input will be ignored. vdd_ref, vdd _pci, vdd_48mhz, vdd_3v66, vdd_cpu 2, 9, 18, 24, 32, 39, 46 p 3.3v power connection: power supply for cpu outputs buffers, 3v66 output buffers, pci output buffers, reference output buffers and 48-mhz output buffers. connect to 3.3v. gnd_pci, gnd_48mhz, gnd_3v66, gnd_cpu, gnd_ref, 5, 13, 21, 29, 36, 43, 47 g ground connection: connect all ground pins to the common system ground plane. vdd_core 34 p 3.3v analog power connection: power supply for core logic, pll circuitry. con- nect to 3.3v. gnd_core 33 g analog ground connection: ground for core logic, pll circuitry. pin definitions (continued) pin name pin no. pin type pin description
preliminary CY28323 document #: 38-07004 rev. *b page 4 of 22 swing select functions multsel1 multsel0 board target trace/term z reference r, iref = vdd/(3*rr) output current v oh @ z 00 50 ? rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.0v @ 50 00 60 ? rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.2v @ 60 01 50 ? rr = 221 1%, iref = 5.00 ma i oh = 5*iref 1.25v @ 50 01 60 ? rr = 221 1%, iref = 5.00 ma i oh = 5*iref 1.5v @ 60 10 50 ? rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.5v @ 50 10 60 ? rr = 221 1%, iref = 5.00 ma i oh = 6*iref 1.8v @ 60 11 50 ? rr = 221 1%, iref = 5.00 ma i oh = 7*iref 1.75v @ 50 11 60 ? rr = 221 1%, iref = 5.00 ma i oh = 7*iref 2.1v @ 60 00 50 ? rr = 475 1%, iref = 2.32 ma i oh = 4*iref 0.47v @ 50 00 60 ? rr = 475 1%, iref = 2.32 ma i oh = 4*iref 0.56v @ 60 01 50 ? rr = 475 1%, iref = 2.32 ma i oh = 5*iref 0.58v @ 50 01 60 ? rr = 475 1%, iref = 2.32 ma i oh = 5*iref 0.7v @ 60 10 50 ? rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.7v @ 50 10 60 ? rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.84v @ 60 11 50 ? rr = 475 1%, iref = 2.32 ma i oh = 7*iref 0.81v @ 50 11 60 ? rr = 475 1%, iref = 2.32 ma i oh = 7*iref 0.97v @ 60
preliminary CY28323 document #: 38-07004 rev. *b page 5 of 22 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions such as individual clock output buffers, etc. can be individually enabled or dis- abled. the register associated with the serial data interface initializ- es to its default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write and block read operation from the controller. for block write/read operation, the bytes must be accessed in se- quential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the sys- tem controller can access individual indexed bytes. the offset of the indexed byte is encoded in the command code, as de- scribed in table 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 1. command code definition bit descriptions 7 0 = block read or block write operation 1 = byte read or byte write operation 6:0 byte offset for byte read or byte write operation. for block read or block write operations, these bits should be ? 0000000 ? . table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ? 00000000 ? stands for block operation 11:18 command code ? 8 bits ? 00000000 ? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge ... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits ... data byte n ? 8 bits 47 acknowledge ... acknowledge from slave 48:55 data byte from slave ? 8 bits ... stop 56 acknowledge ... data bytes from slave/acknowledge ... data byte n from slave ? 8 bits ... not acknowledge ... stop
preliminary CY28323 document #: 38-07004 rev. *b page 6 of 22 data byte configuration map table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code - 8 bits ? 1xxxxxxx ? stands for byte operation bit[6:0] of the command code represents the off- set of the byte to be accessed 11:18 command code - 8 bits ? 1xxxxxxx ? stands for byte operation bit[6:0] of the command code represents the off- set of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop data byte 0 bit pin# name description power on default bit 7 -- spread select2 ? 000 ? = off ? 001 ? = reserved ? 010 ? = reserved ? 011 ? = reserved ? 100 ? = 0.25% ? 101 ? = ? 0.5% ? 110 ? = 0.5% ? 111 ? = 0.38% 0 bit 6 -- spread select1 0 bit 5 -- spread select0 0 bit 4 -- sel4 sw frequency selection bits. see table 4 .0 bit 3 -- sel3 0 bit 2 -- sel2 0 bit 1 -- sel1 0 bit 0 -- sel0 0 data byte 1 bit pin# name description power on default bit 7 38, 37 cpu1, cpu1# (active/inactive) 1 bit 6 41, 40 cpu0, cpu0# (active/inactive) 1 bit 5 22 48mhz (active/inactive) 1 bit 4 23 24_48mhz (active/inactive) 1 bit 3 27 3v66_3 (active/inactive) 1
preliminary CY28323 document #: 38-07004 rev. *b page 7 of 22 bit 2 28 3v66_2 (active/inactive) 1 bit 1 30 3v66_1 (active/inactive) 1 bit 0 31 3v66_0 (active/inactive) 1 data byte 1 (continued) bit pin# name description power on default data byte 2 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 17 pci6 (active/inactive) 1 bit 5 16 pci5 (active/inactive) 1 bit 4 15 pci4 (active/inactive) 1 bit 3 14 pci3 (active/inactive) 1 bit 2 12 pci2 (active/inactive) 1 bit 1 11 pci1 (active/inactive) 1 bit 0 10 pci0 (active/inactive) 1 data byte 3 bit pin# name pin description power on default bit 7 8 pci_f2 (active/inactive) 1 bit 6 7 pci_f1 (active/inactive) 1 bit 5 6 pci_f0 (active/inactive) 1 bit 4 -- reserved reserved 0 bit 3 44, 45 cpu_itp, cpu_itp# (active/inactive) 1 bit 2 -- reserved reserved 0 bit 1 1 ref1 (active/inactive) 1 bit 0 48 ref0 (active/inactive) 1 data byte 4 bit pin# name pin description power on default bit 7 -- multsel_override this bit control the selection of iref multiple. 0 = hw control; iref multiplier is determined by multsel[0:1] input pins 1 = sw control; iref multiplier is determined by byte[4], bit[5:6]. 0 bit 6 -- sw_multsel1 iref multiplier 00 = ioh is 4 x iref 01 = ioh is 5 x iref 10 = ioh is 6 x iref 11 = ioh is 7 x iref 0 bit 5 -- sw_multsel0 0 bit 4 -- reserved reserved reserved bit 3 -- reserved reserved reserved bit 2 -- reserved reserved reserved bit 1 -- reserved reserved reserved bit 0 -- reserved reserved reserved
preliminary CY28323 document #: 38-07004 rev. *b page 8 of 22 data byte 5 bit pin# name pin description power on default bit 7 10 latched fs4 input latched fs[4:0] inputs. these bits are read only. x bit 6 7 latched fs3 input x bit 5 6 latched fs2 input x bit 4 23 latched fs1 input x bit 3 22 latched fs0 input x bit 2 -- fs_override 0 = select operating frequency by fs[4:0] input pins 1 = select operating frequency by sel[4:0] settings 0 bit 1 -- reserved reserved 0 bit 0 23 sel 48mhz 0 = 24 mhz 1 = 48 mhz 0 data byte 6 bit pin# name pin description power on default bit 7 revision_id3 revision id bit[3] 0 bit 6 revision_id2 revision id bit[2] 0 bit 5 revision_id1 revision id bit[1] 0 bit 4 revision_id0 revision id bit[0] 0 bit 3 vendor_id3 bit[3] of cypress semiconductor ? s vendor id. this bit is read-only. 1 bit 2 vendor_id2 bit[2] of cypress semiconductor ? s vendor id. this bit is read-only. 0 bit 1 vendor _id1 bit[1] of cypress semiconductor ? s vendor id. this bit is read-only. 0 bit 0 vendor _id0 bit[0] of cypress semiconductor ? s vendor id. this bit is read-only. 0 data byte 7 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 -- reserved reserved 0
preliminary CY28323 document #: 38-07004 rev. *b page 9 of 22 data byte 8 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- wd_timer4 these bits store the time-out value of the watchdog timer. the scale of the timer is determine by the prescaler. the timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. if the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. when the watchdog timer reaches ? 0, ? it will set the wd_to_status bit and generate reset if rst_en_wd is enabled. 1 bit 4 -- wd_timer3 1 bit 3 -- wd_timer2 1 bit 2 -- wd_timer1 1 bit 1 -- wd_timer0 1 bit 0 -- wd_pre_scaler 0 = 150 ms 1 = 2.5 sec 0 data byte 9 bit pin# name pin description power on default bit 7 -- 48mhz_drv 48-mhz & 24_48-mhz clock output drive strength 0 = normal 1 = high drive (recommend to set to high drive if this output is being used to drive both usb and sio devices in intel ? brookdale - g platforms) 0 bit 6 -- pci_drv pci clock output drive strength 0 = normal 1 = high drive 0 bit 5 -- 3v66_drv 3v66 clock output drive strength 0 = normal 1 = high drive 0 bit 4 -- rst_en_wd this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled 0 bit 3 -- rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled 0 bit 2 -- wd_to_status watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write) 0 bit 1 -- wd_en 0 = stop and reload watchdog timer 1 = enable watchdog timer. it will start counting down after a frequency change occurs. note: CY28323 will generate system reset, reload a recov- ery frequency, and lock itself into a recovery frequency mode after a watchdog timer time-out occurs. under re- covery frequency mode, CY28323 will not respond to any attempt to change output frequency via the smbus control bytes. system software can unlock CY28323 from its re- covery frequency mode by clearing the wd_en bit. 0 bit 0 -- reserved reserved 0
preliminary CY28323 document #: 38-07004 rev. *b page 10 of 22 data byte 10 bit pin# name pin description power on default bit 7 -- cpu_skew2 cpu skew control 000 = normal 001 = ? 150 ps 010 = ? 300 ps 011 = ? 450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps 0 bit 6 -- cpu_skew1 0 bit 5 -- cpu_skew0 0 bit 4 -- reserved reserved 0 bit 3 -- pci_skew1 pci skew control 00 = normal 01 = ? 500 ps 10 = reserved 11 = +500 ps 0 bit 2 -- pci_skew0 0 bit 1 -- 3v66_skew1 3v66 skew control 00 = normal 01 = ? 150 ps 10 = +150 ps 11 = +300 ps 0 bit 0 -- 3v66_skew0 0 data byte 11 bit pin# name pin description power on default bit 7 -- rocv_freq_n7 if rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be use to determine the recovery cpu output frequency when a watchdog timer time-out occurs. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when the fs_override bit is cleared, the same frequency ratio stat- ed in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 6 -- rocv_freq_n6 0 bit 5 -- rocv_freq_n5 0 bit 4 -- rocv_freq_n4 0 bit 3 -- rocv_freq_n3 0 bit 2 -- rocv_freq_n2 0 bit 1 -- rocv_freq_n1 0 bit 0 -- rocv_freq_n0 0 data byte 12 bit pin# name pin description power on default bit 7 -- rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the clock generator will automatically switch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_freq_n[7:0] & rocv_freq_m[6:0] 0
preliminary CY28323 document #: 38-07004 rev. *b page 11 of 22 bit 6 -- rocv_freq_m6 if rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be use to determine the recovery cpu output frequen- cy.when a watchdog timer time-out occurs. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when the fs_override bit is cleared, the same frequency ratio stat- ed in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 5 -- rocv_freq_m5 0 bit 4 -- rocv_freq_m4 0 bit 3 -- rocv_freq_m3 0 bit 2 -- rocv_freq_m2 0 bit 1 -- rocv_freq_m1 0 bit 0 -- rocv_freq_m0 0 data byte 12 (continued) bit pin# name pin description power on default data byte 13 bit pin# name pin description power on default bit 7 -- cpu_fsel_n7 if prog_freq_en is set, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] will be used to determine the cpu output frequency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of the fs_override bit determines the frequen- cy ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 6 -- cpu_fsel_n6 0 bit 5 -- cpu_fsel_n5 0 bit 4 -- cpu_fsel_n4 0 bit 3 -- cpu_fsel_n3 0 bit 2 -- cpu_fsel_n2 0 bit 1 -- cpu_fsel_n1 0 bit 0 -- cpu_fsel_n0 0 data byte 14 bit pin# name pin description power on default bit 7 -- pro_freq_en programmable output frequencies enabled 0 = disabled 1 = enabled 0 bit 6 -- cpu_fsel_m6 if prog_freq_en is set, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] will be used to determine the cpu output frequency. the new frequency will start to load whenever cpu_fselm[6:0] is updated. the setting of the fs_override bit determines the frequen- cy ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 0 bit 5 -- cpu_fsel_m5 0 bit 4 -- cpu_fsel_m4 0 bit 3 -- cpu_fsel_m3 0 bit 2 -- cpu_fsel_m2 0 bit 1 -- cpu_fsel_m1 0 bit 0 -- cpu_fsel_m0 0 data byte 15 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0
preliminary CY28323 document #: 38-07004 rev. *b page 12 of 22 bit 1 -- vendor test mode reserved. write with ? 1 ? 1 bit 0 -- vendor test mode reserved. write with ? 1 ? 1 data byte 15 (continued) bit pin# name pin description power on default data byte 16 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 -- reserved reserved 0 data byte 17 bit pin# name pin description power on default bit 7 -- reserved reserved 0 bit 6 -- reserved reserved 0 bit 5 -- reserved reserved 0 bit 4 -- reserved reserved 0 bit 3 -- reserved reserved 0 bit 2 -- reserved reserved 0 bit 1 -- reserved reserved 0 bit 0 -- reserved reserved 0
preliminary CY28323 document #: 38-07004 rev. *b page 13 of 22 table 4. frequency selection table input conditions output frequency pll gear constants (g) fs4 fs3 fs2 fs1 fs0 cpu 3v66 pci sel4 sel3 sel2 sel1 sel0 0 0 0 0 0 102.0 68.0 34.0 48.00741 0 0 0 0 1 105.0 70.0 35.0 48.00741 0 0 0 1 0 108.0 72.0 36.0 48.00741 0 0 0 1 1 111.0 74.0 37.0 48.00741 0 0 1 0 0 114.0 76.0 38.0 48.00741 0 0 1 0 1 117.0 78.0 39.0 48.00741 0 0 1 1 0 120.0 80.0 40.0 48.00741 0 0 1 1 1 123.0 82.0 41.0 48.00741 0 1 0 0 0 126.0 63.0 31.5 48.00741 0 1 0 0 1 130.0 65.0 32.5 48.00741 0 1 0 1 0 136.0 68.0 34.0 48.00741 0 1 0 1 1 140.0 70.0 35.0 48.00741 0 1 1 0 0 144.0 72.0 36.0 48.00741 0 1 1 0 1 148.0 74.0 37.0 48.00741 0 1 1 1 0 152.0 76.0 38.0 48.00741 0 1 1 1 1 156.0 78.0 39.0 48.00741 1 0 0 0 0 160.0 80.0 40.0 48.00741 1 0 0 0 1 164.0 82.0 41.0 48.00741 1 0 0 1 0 166.6 66.6 33.3 48.00741 1 0 0 1 1 170.0 68.0 34.0 48.00741 1 0 1 0 0 175.0 70.0 35.0 48.00741 1 0 1 0 1 180.0 72.0 36.0 48.00741 1 0 1 1 0 185.0 74.0 37.0 48.00741 1 0 1 1 1 190.0 76.0 38.0 48.00741 1 1 0 0 0 66.8 66.8 33.4 48.00741 1 1 0 0 1 100.2 66.8 33.4 48.00741 1 1 0 1 0 133.6 66.8 33.4 48.00741 1 1 0 1 1 200.4 66.8 33.4 48.00741 1 1 1 0 0 66.6 66.6 33.3 48.00741 1 1 1 0 1 100.0 66.6 33.3 48.00741 1 1 1 1 0 200.0 66.6 33.3 48.00741 1 1 1 1 1 133.3 66.6 33.3 48.00741
preliminary CY28323 document #: 38-07004 rev. *b page 14 of 22 programmable output frequency, watchdog timer and recovery output frequency functional description the programmable output frequency feature allows users to generate any cpu output frequency in the range of 50 mhz to 248 mhz. cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. the watchdog timer and recovery output frequency fea- tures allow users to implement a recovery mechanism when the system hangs or getting unstable. system bios or other control software can enable the watchdog timer before they attempt to make a frequency change. if the system hangs and a watchdog timer time-out occurs, a system reset will be gen- erated and a recovery frequency will be activated. all the related registers are summarized in table 5 . table 5. register summary name description pro_freq_en programmable output frequencies enabled 0 = disabled (default) 1 = enabled when it is disabled, the operating output frequency will be determined by either the latched value of fs[4:0] inputs or the programmed value of sel[4:0]. if the fs_override bit is clear, latched fs[4:0] inputs will be used. if the fs_override bit is set, the programmed value of sel[4:0] will be used. when it is enabled, the cpu output frequency will be determined by the programmed value of cpufsel_n, cpufsel_m and the pll gear constant. the program value of fs_override, sel[4:0] or the latched value of fs[4:0] will determine the pll gear constant and the frequency ratio between cpu and other frequency outputs fs_override when pro_freq_en is cleared or disabled, 0 = select operating frequency by fs input pins (default) 1 = select operating frequency by sel bits in smbus control bytes when pro_freq_en is set or enabled, 0 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the latched value of fs input pins (default) 1 = frequency output ratio between cpu and other frequency groups and the pll gear constant are based on the programmed value of sel bits in smbus control bytes cpu_fsel_n, cpu_fsel_m when prog_freq_en is set or enabled, the values programmed in cpu_fsel_n[7:0] and cpu_fsel_m[6:0] determines the cpu output frequency. the new frequency will start to load when- ever there is an update to either cpu_fsel_n[7:0] or cpu_fsel_m[6:0]. therefore, it is recom- mended to use word or block write to update both registers within the same smbus bus operation. the setting of fs_override bit determines the frequency ratio for cpu, agp and pic. when fs_override is cleared or disabled, the frequency ratio follows the latched value of the fs input pins. when fs_override is set or enabled, the frequency ratio follows the programmed value of sel bits in smbus control bytes. rocv_freq_sel rocv_freq_sel determines the source of the recover frequency when a watchdog timer time-out occurs. the clock generator will automatically switch to the recovery cpu frequency based on the selection on rocv_freq_sel. 0 = from latched fs[4:0] 1 = from the settings of rocv_freq_n[7:0] & rocv_freq_m[6:0] rocv_freq_n[7:0], rocv_freq_m[6:0] when rocv_freq_sel is set, the values programmed in rocv_freq_n[7:0] and rocv_freq_m[6:0] will be used to determine the recovery cpu output frequency when a watchdog timer time-out occurs the setting of the fs_override bit determines the frequency ratio for cpu, agp and pic. when it is cleared, the same frequency ratio stated in the latched fs[4:0] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. the new frequency will start to load whenever there is an update to either rocv_freq_n[7:0] and rocv_freq_m[6:0]. therefore, it is recommended to use word or block write to update both regis- ters within the same smbus bus operation. wd_en 0 = stop and reload watchdog timer 1 = enable watchdog timer. it will start counting down after a frequency change occurs.
preliminary CY28323 document #: 38-07004 rev. *b page 15 of 22 program the cpu output frequency when the programmable output frequency feature is enabled (pro_freq_en bit is set), the cpu output frequency is deter- mined by the following equation: fcpu = g * (n+3)/(m+3) ? n ? and ? m ? are the values programmed in programmable fre- quency select n-value register and m-value register, re- spectively. ? g ? stands for the pll gear constant, which is determined by the programmed value of fs[4:0] or sel[4:0]. the value is listed in table 4 . the ratio of (n+3) and (m+3) need to be greater than ? 1 ? [(n+3)/(m+3) > 1]. the following table lists set of n and m values for different frequency output ranges.this example use a fixed value for the m-value register and select the cpu output frequency by changing the value of the n-value register. wd_to_status watchdog timer time-out status bit 0 = no time-out occurs (read); ignore (write) 1 = time-out occurred (read); clear wd_to_status (write) wd_timer[4:0] these bits store the time-out value of the watchdog timer. the scale of the timer is determine by the prescaler. the timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. if the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. when the watchdog timer reaches ? 0 ? , it will set the wd_to_status bit. wd_pre_scaler 0 = 150 ms 1 = 2.5 sec rst_en_wd this bit will enable the generation of a reset pulse when a watchdog timer time-out occurs. 0 = disabled 1 = enabled rst_en_fc this bit will enable the generation of a reset pulse after a frequency change occurs. 0 = disabled 1 = enabled table 5. register summary (continued) name description table 6. examples of n and m value for different cpu frequency range frequency ranges gear constants fixed value for m-value register range of n-value register for different cpu frequency 50 mhz ? 129 mhz 48.00741 93 97 ? 255 130 mhz ? 248 mhz 48.00741 45 127 ? 245
preliminary CY28323 document #: 38-07004 rev. *b page 16 of 22 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage ................................................. ? 0.5 to +7.0v input voltage ............................................ ? 0.5v to v dd + 0.5 storage temperature (non-condensing) ... ? 65 c to +150 c max. soldering temperature (10 sec) ...................... +260 c junction temperature ............................................... +150 c package power dissipation...............................................1 ? static discharge voltage (per mil-std-883, method 3015) ............................. >2000v operating conditions [2] over which electrical parameters are guaranteed parameter description min. max. unit v dd_ref , v dd_pci ,v dd_core , v dd_3v66 , v dd_48 mhz, v dd_cpu, 3.3v supply voltages 3.135 3.465 v t a operating temperature, ambient 0 70 c c in input pin capacitance 5 pf c xtal xtal pin capacitance 22.5 pf c l max. capacitive load on 48mhz, ref pciclk, 3v66 20 30 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz electrical characteristics over the operating range parameter description test conditions min. max. unit v ih high-level input voltage except crystal pads. threshold voltage for crystal pads = v dd /2 2.0 v v il low-level input voltage except crystal pads 0.8 v v oh high-level output voltage 48mhz, ref, 3v66 i oh = ? 1 ma 2.4 v pci i oh = ? 1 ma 2.4 v v ol low-level output voltage 48mhz, ref, 3v66 i ol = 1 ma 0.4 v pci i ol = 1 ma 0.55 v i ih input high current 0 < v in < v dd ? 55ma i il input low current 0 < v in < v dd ? 55ma i oh high-level output current cpu for i oh = 6*iref configuration type x1, v oh = 0.65v 12.9 ma type x1, v oh = 0.74v 14.9 ref, 48 mhz type 3, v oh = 1.00v ? 29 type 3, v oh = 3.135v ? 23 3v66, pci type 5, v oh = 1.00v ? 33 type 5, v oh = 3.135v ? 33 i ol low-level output current ref, 48mhz type 3, v ol = 1.95v 29 ma type 3, v ol = 0.4v 27 3v66, pci, type 5, v ol =1.95 v 30 type 5, v ol = 0.4v 38 i oz output leakage current three-state 10 ma i dd3 3.3v power supply current v dd_core /v dd33 = 3.465v, f cpu = 133 mhz 250 ma i ddpd3 3.3v shutdown current v dd_core / vddq3 = 3.465v 20 ma notes: 2. multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required.
preliminary CY28323 document #: 38-07004 rev. *b page 17 of 22 - switching characteristics [[3]] over the operating range parameter output description test conditions min. max. unit t 1 all output duty cycle [[4]] t 1a /(t 1b ) 45 55 % t 2 cpu rise time measured at 20% to 80% of v oh 175 700 ps t 2 48mhz, ref rising edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 2 pci, 3v66, rising edge rate between 0.4v and 2.4v 1.0 4.0 v/ns t 3 cpu fall time measured at 80% to 20% of v oh 175 700 ps t 3 48mhz, ref falling edge rate between 2.4v and 0.4v 0.5 2.0 v/ns t 3 pci, 3v66 falling edge rate between 2.4v and 0.4v 1.0 4.0 v/ns t 4 cpu cpu-cpu skew measured at crossover 150 ps t 5 3v66 [0:1] 3v66-3v66 skew measured at 1.5v 500 ps t 6 pci pci-pci skew measured at 1.5v 500 ps t 7 3v66,pci 3v66-pci clock skew 3v66 leads. measured at 1.5v 1.5 3.5 ns t 8 cpu cycle-cycle clock jitter measured at crossover t 8 = t 8a ? t 8b with all outputs running 200 ps t 9 3v66 cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 250 ps t 9 48mhz cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 350 ps t 9 pci cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 500 ps t 9 ref cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 1000 ps cpu, pci settle time cpu and pci clock stabilization from power-up 3 ms cpu rise/fall matching measured with test loads [[5], [6]] 20% cpu overshoot measured with test loads [[6]] v oh + 0.2 v cpu undershoot measured with test loads [[6]] ? 0.2 v v oh cpu high-level output voltage measured with test loads [[6]] 0.65 0.74 v v ol cpu low-level output voltage measured with test loads [[6]] 0.0 0.05 v v crossover cpu crossover voltage measured with test loads [[6]] 45% of 0.65 55% of 0.74 v notes: 3. all parameters specified with loaded outputs. 4. duty cycle is measured at 1.5v when v dd = 3.3v. when v dd = 2.5v, duty cycle is measured at 1.25v. 5. determined as a fraction of 2*(t rp ? t rn )/(t rp + t rn ) where t rp is a rising edge and t rn is an intersecting falling edge. 6. the test load is r s = 33.2 ? , r p = 49.9 ? in test circuit.
preliminary CY28323 document #: 38-07004 rev. *b page 18 of 22 switching waveforms duty cycle timing t 1b (single ended output) t 1a duty cycle timing (cpu differential output) t 1b t 1a all outputs rise/fall time output t 2 v dd 0v t 3 cpu-cpu clock skew host_b host t 4 host_b host 3v66-3v66 clock skew 3v66 3v66 t 5
preliminary CY28323 document #: 38-07004 rev. *b page 19 of 22 switching waveforms (continued) pci-pci clock skew pci pci t 6 3v66 pci t 7 3v66-pci clock skew t 8a t 8b cpu clock cycle-cycle jitter host_b host t 9a t 9b cycle-cycle clock jitter clk ordering information ordering code package type operating range CY28323pvc 48-pin small shrunk outline package (ssop) commercial
preliminary CY28323 document #: 38-07004 rev. *b page 20 of 22 layout example g fb +3.3v supply 0.005 f g g vddq3 c3 CY28323 48 47 46 45 44 43 42 41 40 38 37 36 35 34 3 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 g v g v g v g v g v g v g v g g 5 ? vddq3 c5 c6 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors cermaic caps c3 = 10 ? 22 f c4 = 0.005 f fb = dale ilb1206 - 300 (300 ? @ 100 mhz) c5 = 10 f c6 = 0.1 f all bypass caps = 0.1 f ceramic * for use with onboard video using 48 mhz for dot clock or connect to vddq3 * g g g g g g g g g g g g g g g g g g g g
CY28323 preliminary document #: 38-07004 rev. *b page 21 of 22 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 48-lead shrunk small outline package o48 51-85061-c
preliminary CY28323 document #: 38-07004 rev. *b page 22 of 22 document title: CY28323 ftg for intel pentium 4 cpu and chipsets document number: 38-07004 rev. ecn no. issue date orig. of change description of change ** 106090 06/27/01 ika new data sheet *a 110677 11/15/01 ika revised 2nd bullet on page 1 (add ? 845 ? to first brookdale, bookdale-g to brookdale-g) *b 122712 12/14/02 rbi added power up requirements to operating conditions information.

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